1. Field of the Invention
The present invention relates to a delay-locked loop (DLL), and more particularly to a DLL, an integrated circuit (IC) incorporating a DLL, and a method of driving a DLL capable of reliable operation in spite of an incident duty error.
2. Description of the Related Art
Contemporary electronic and telecommunications equipment require very precise transmission of various signals in order to operate properly. Hence, it is critical to accurately reproduce the timing characteristics of the signals in order to ensure their proper transmission and reception. That is, the signals must typically be synchronized in their transmission and reception with a standard or reference timing signal (e.g., a clock reference signal). The phase-locked loop (PLL) and the delay-locked loop (DLL) are circuits commonly used to synchronize the timing characteristics between signals.
The conventional PLL generates a voltage control signal corresponding to a phase difference between an external clock signal and a reproduction clock signal. The phase of the reproduction clock signal is adjusted in relation to the voltage control signal to follow the phase of the external clock signal by means of varying the frequency of the reproduction clock signal.
The conventional DLL similarly generates a voltage control signal corresponding to a phase difference between the external clock signal and the reproduction clock signal, but adjusts a delay period for the reproduction clock signal in response to the voltage control signal to thereby control the phase of the reproduction clock signal such that it follows the phase of the external clock signal.
A DLL is commonly used in digital signal processing systems and synchronous memory devices, such as Dynamic Random Access Memory (DRAM). Common DLL configurations use an inversion scheme that provides a fast locking of signals at the beginning of a phase locking operation.
Referring to Figure (FIG.) 1, a typical inversion scheme, as implemented in a DLL circuit, compares the phase of a received external clock signal (EXCLK) with the phase of a reproduction clock signal (RCLK) in order to generate (i.e., “output”) the received external clock signal RCLK without inversion when the phase difference, τ1, between the clock signals EXCLK and RCLK is greater than one half of a cycle, (i.e., T/2(τ1>T/2) ). (See timing relationship (iii) in FIG. 1). In contrast, an inverted reproduction clock signal (RCLKB) is output when the phase difference, τ2, is less than one half of a cycle (i.e., T/2(τ2<T/2) ). (See timing relationship (ii) in FIG. 1). Within the foregoing timing relationships, the “following time” (i.e., a delay time) required to lock the rising edge of RCLK to the rising edge of EXCLK can be reduced to no more than half a clock cycle.
However, this is not the case where the duty cycle ratio of RCLK falls below 50%. (See timing relationship (i) in FIG. 1). In such cases, the reproduction clock signal ERCLK must be delayed by more than half a cycle when inversion is performed because otherwise the phase difference during the next cycle would be mistakenly seen as being less than a half cycle despite the phase difference actually being more than a half cycle.
Thus, a DLL implementing the foregoing inversion scheme experiences a problem in that the initial locking time is additionally delayed by as much as the change in the duty ratio of the reproduction clock signal RCLK. Operating speed suffers accordingly when one cycle of the clock signal is larger than a predetermined maximum delay period, and phase unlocking may occur because an appropriate locking delay adjustment cannot be performed for such delay periods.